IBM on Thursday unveiled the world’s first sub-1 nanometer chip technology, a research prototype at the 0.7 nanometer node that packs nearly 100 billion transistors onto a chip the size of a fingernail.
Key Takeaways:
IBM’s nanostack chip at the 0.7 nm node packs nearly 100 billion transistors, nearly 2x the density of IBM’s 2021 chip.The 3D architecture delivers up to 70% greater energy efficiency, targeting artificial intelligence (AI) accelerator workloads with improved SRAM scaling of 40%.IBM Research sees a path to production in five years and projects that the nanostack design supports at least a decade of continued semiconductor scaling.That approach differs fundamentally from the nanosheet technology IBM pioneered and the broader industry adopted. Nanosheets compressed features in two dimensions. Nanostack adds density in a third.
“We’re not just making smaller transistors, we’re reinventing how chips are built to deliver dramatically more power and energy efficiency,” said Jay Gambetta, Director of IBM Research and IBM Fellow.
What the Numbers ShowIBM’s published technical results, presented at VLSI 2026, report the following compared to IBM’s 2 nm chip from 2021:
Nearly 2x transistor density Up to 50% more performance Up to 70% greater energy efficiency 40% improvement in SRAM scaling Why the 0.7 nm Label Needs Context A Path Forward for Moore’s LawThe semiconductor industry has faced mounting pressure as traditional two-dimensional shrinking hits physical constraints, including quantum tunneling, heat dissipation, and manufacturing cost. The pace of gains from pure lithography improvements has slowed.
IBM’s approach addresses this by adding density through 3D sequential integration. The company projects the nanostack architecture can support at least a decade of continued scaling from this point.
Major competitors like Intel, Samsung, and TSMC are pursuing related three-dimensional transistor strategies, including complementary FET designs. IBM’s announcement represents a working demonstration of a verified path at the sub-1 nm threshold.
The Albany Research EcosystemIBM conducts this work alongside partners including Lam Research, Tokyo Electron, and SCREEN Semiconductor Solutions. The Albany facility will also house a High Numerical Aperture Extreme Ultraviolet lithography tool from ASML, a system required for the next phase of logic scaling.
IBM separately announced plans to form Anderon, a standalone quantum foundry intended to manufacture quantum wafers at commercial scale.
Timeline to ProductionThe nanostack chip remains a research prototype, though IBM confirmed it has demonstrated functional CMOS inverter operation with expected switching performance. IBM sees a path to production adoption in as early as five years, or roughly 2031.
The announcement does not signal an imminent product release. It signals that the industry’s next generation of hardware has a viable structural foundation.
